We are actively seeking a Silicon Design Framework and Emulation-Prototyping Staff Engineer to join our dynamic and growing Hardware Design team.
Job Description:
You will work in synergy with Hardware Validation, Architecture and Software teams to:
- Develop and Implement Emulation & Prototyping strategies based on product goals and KPIs
- Enable Accelerated HW Validation, Compliance testing and Stress Testing using Emulation platforms
- Enable Hardware aware Software Development and Debug on Emulation and Prototyping Platforms
- Contribute to the definition and maintenance of Virtual Platforms for SW development, Co-Emulation (Hybrid platforms), SW driven HW Verification and Architectural Exploration
- Develop and maintain Emulation, Prototyping and Virtual Prototyping Frameworks to enable the Performance and Power Analysis of the SoC
Minimum Qualifications:
- HDL and HVL Languages (Verilog, System Verilog, C/C++, SystemC, VHDL)
- UVM methodology and Testbench construction, Functional Coverage and Verilog Assertions, Verification IPs
- EDA Tools for digital simulation (Questa, VCS, Xcelium) and Debug (Visualizer, Verdi, Verisium)
- Direct Experience with Commercial Emulation Platforms (Synopsys Zebu EP1/2, Cadence Palladium Z1/Z2, Siemens Veloce Strato+) or Prototyping Platforms (Synopsys HAPS-80/100, Cadence Protium X1/X2, Siemens Primo, Primo CS, ProFPGA, ProFPGA CS)
- Direct experience in developing/setting-up custom or commercial transactors for interfacing System Verilog UVM Testbench or SystemC TLM Virtual Platforms with Emulation platforms
- System / Functional Modeling Languages (C,C++, SystemC TLM LT/AT)
- Direct experience in constructing virtual platforms for SW development, architectural exploration, co-emulation. Experience with Commercial Virtual Prototyping platforms (Synopsys Platform Architect, Virtualizer or Cadence Helium or Siemens NextGen/Vista) or other opensource frameworks like Gem5
- Experience in Processors Compliance Testing, ISS simulators & reference models (Spike, riscvOVPsim), Stress Tests, Benchmarking and other commercial processor centric functional verification siutes (Sting, ImperasDV)
- Familiarity with high performance coherent on-chip & chiplet to chiplet communication protocols (AXI-ACE, CHI, CXL), interfaces (PCIe, UCIe), debug interfaces/protocols (JTAG, ATB, TPIU etc…) cache coherency, interfaces to High Performance Memory Systems (HBM controller/PHY) is much appreciated
- Experience with RISC-V toolchain and ISA is a plus
- At least 10 years of past experience developing in SoC Design and MS in EE, CE, CS or a related technical discipline.
Soft skills
- The candidate should be equipped with a unique skills-set: Self-starter, self-motivated, humility, excellent communications skills; outstanding human qualities as honesty, integrity, fellowship, generosity and commitment with his/her mission to change the world.
- Excellent communication and management skills
- He/she is a natural team player with the aim to create a positive impact in the society.
What do we offer?
- Join an innovative team and experience company growth.
- We believe in investing in our employees and providing them with the opportunities they need to grow and develop their careers.
- Enjoy a hybrid work environment.
- We also offer flexible schedule.
- We offer a remuneration that values your experience.
- The position will have the base in Barcelona or Rome.
We are looking for outstanding people willing to join our mission to change this industry and help to build a better world.
If you feel identified with Openchip, please contact us. We can offer a competitive compensation package in a flexible work schema that will help you to keep a balance between your personal and professional life.
At Openchip & Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.
