The Role:
We seek an experienced place-and-route engineer to manage complex digital backend flows. The role requires interfacing digital front-end designers to understand the requirements that come from RTL synthesis and to be able to partition architectures to give inputs at the generation of rational floorplanning and to drive physical aspects early in the design cycle.
Responsibilities:
- Assure the deliverability of the main part of the chip;
- Taking care of P&R/STA flows and tools available in the latest industry;
- Meaning of the synthesis and capability to drive place and route of complex blocks through signoff flows including timing and physical verification.
- Drive Place & Route in chip-level and hierarchical physical implementation environment taking care of the floorplan with critical mind.
- Running MBIST and DFT insertion into block, understanding impact of MBIST/Scan and debug logic is desirable.
- Continue interaction with RTL designers to resolve design issues on block closure and reach and assure power/performance/area targets.
Qualifications:
- Master’s degree in Electrical Engineering, Electronics Engineering or 7+ experience in the field;
- Experience in physical design flow including gate level netlist, floor planning, partitioning, power planning, placement, synthesis, clock & power distribution, timing closure and routing;
- Synthesis fundamentals;
- Timing analysis deep comprehension;
- Test bench development;
- DRC/LVS and parasitic extraction capability.
The person should be in Barcelona or Italy.
Soft skills
- We are looking for team players who focus on the outcome of the team above the individual needs, with respect and honest challenge.
- Within- and cross-team collaboration at the technical level.
- The ideal candidate should count on a “can-do attitude”, willing to solve any obstacle by himself. Self-starter and self-motivated.
