The SoC Architecture team is responsible for defining high-performance and power efficient System-on-Chip hardware architecture.
The team identifies Hardware Requirements, defines the overall SoC system and delivers High-level Architecture Specification (HAS) integrating multiple processing units, memory, interconnects, accelerators, interfaces and peripherals to achieve optimal Power, Performance, Area and Cost (PPAC) efficiency. The team is also responsible for overall aspects of security, debug, production test and device packaging and for defining and maintaining Configuration Management processes for scalable and configurable architectures.
The team works closely with Product, Technology, Software and AI, and Hardware Engineering Teams for Design Implementation and Verification.
The Role:
The ideal candidate should have strong knowledge of hardware architectures, VLSI design, and successful industry experience with deployment of IPs in large SoC while working in a collaborative environment. This is a Hardware Architecture role that emphasizes a strong focus on defining and integrating Reliability, Availability and Serviceability (RAS) requirements and features for a resilient Hardware Architecture.
This role requires proactive collaboration with security experts and teams involved in Hardware Implementation, Software, System, and Product security. You will be responsible for all aspects of Hardware Security, throughout the Concept, Definition, and Specification of Hardware Architecture.
Key responsibilities:
Architect and define overall SoC including processing units, hardware accelerators, memory, interconnect, interfaces and analog components.
Work hand in hand with the product architects making sure hardware architecture meets the product goals.
Define RAS strategies, support the architecture of RAS features and the intersection of RAS with all aspects of Hardware Design and Software implementation.
Development of hardware architecture models and simulations that include RAS metrics (e.g. Failure in Time for permanent and transient errors and Architecture Vulnerability Factor (AVF)).
Evaluation of architectural and micro-architecture options including different levels of protection and protection mechanisms (e.g. Error Correction Code, parity, redundancy) and the impacts in Power Performance, Area and Cost (PPAC).
Conduct system-level modelling and analysis to optimise for power, performance, area and cost.
Work with Software and Firmware teams for efficient and optimal system codesign.
Evaluate new processes, technologies, trends, and industry standards.
Perform hard and soft IP identification, analysis and selection.
Lead architecture definition, reviews and provide technical guidance.
Work with peer micro architects across the organization aligning product and architecture definition.
Collaborate with design implementation, verification, physical design, software and firmware teams for development and design convergence.
Support SoC execution across project milestones working with all crossfunctional teams to identify and drive complex dependencies resolution.
Define and develop system-level methodologies, tools, and IPs to build SoCs in an efficient and scalable manner.
This role requires a talent for cross-functional collaboration, where effective communication and engagement are essential throughout the entire Product Development process, with a strong emphasis on reliability.
Qualifications:
Bachelor’s/Master’s/PhD in Electrical Engineering, Computer Engineering or related field 10+ years of solid experience in IP/SoC architecture and design for ASIC or FPGA.
Foundational understanding and familiarity with key reliability themes is desired, including: Error detection and correction codes as ECC, CRC, parity, Reed-Solomon, BCH).
Fault isolation, failover, redundancy mechanisms (spare cores, redundant memory channels, retry logic, watchdog timers).
Familiarity with serviceability features such as logging, telemetry, and predictive failure analysis.
Experience with thermal, voltage, and aging-related failures.
Good knowledge on Design for Testability and Manufacturability and the intersection with RAS.
Experience with architecture trade-offs and design methodologies for optimal performance power area cost (PPAC) in advanced technologies.
Proficiency in performance modelling, simulation frameworks and scripting.
Strong knowledge and industry expertise in multiple aspects of SoC architecture definition such as Clocks, Resets, Power-Sequencing, Power Management, Interrupts, Interconnects, Boot, Virtualization, Security, System Performance, IO technologies, Platform integration.
Experience with RISC-V based Systems.
General knowledge of SoC implementation standards, interconnect (AMBA, AXI, CHI) and interfaces (PCIe, UCIe, I2C, I3C, SPI, JTAG).
General knowledge of Advanced packaging (2.5D, 3D, SiP, CoWoS) and chiplets.
What do we offer?
Join an innovative team and experience company growth.
We believe in investing in our employees and providing them with the opportunities they need to grow and develop their careers.
Enjoy a hybrid work environment.
We also offer flexible schedule.
We offer a remuneration that values your experience.
The position will be based in Barcelona.
We are looking for outstanding people willing to join our mission to change this industry and help to build a better world.
If you feel identified with Openchip, please contact us. We can offer a competitive compensation package in a flexible work schema that will help you to keep a balance between your personal and professional life.
At Openchip & Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.