The Role:
Evaluate Openchip’s RISC-V platforms for performance, power efficiency, and scalability using HLRS workloads. You’ll be based at Openchip, collaborating virtually with HLRS for workload curation and validation (optional short visits possible).
Key Responsibilities:
Plan and execute controlled benchmarks on Openchip RISC-V boards/simulators/FPGA prototypes.
Analyze strong/weak scaling, bandwidth sensitivity, cache/NUMA effects, and vector/ISA utilization.
Model energy-to-solution and performance/W; compare against established baselines. Optimize kernels (compiler flags, vectorization, memory placement) and quantify gains.
Produce a prioritized co-design brief (ISA/runtime/compiler/hardware) backed by evidence.
Qualifications:
Pursuing MSc in Computer Science, Computer Engineering, Electronics Engineering, or related field.
Proficient in C/C++ and Python; comfortable with build systems and benchmarking.
Knowledge of performance analysis (roofline, CPI stacks, Amdahl/Gustafson).
Familiarity with MPI/OpenMP and systems fundamentals.
Strong technical writing for reproducible reports.
Preferred qualifications:
RISC-V ISA (incl. Vector) and LLVM/GCC toolchains.
Autotuning, kernel optimization, or numerical libraries experience.
gem5, RTL/FPGA flows, or basic power/perf modeling.
Track record of patches/RFCs/spec proposals.
We are looking for exceptional individuals ready to build the infrastructure backbone for the future of AI. If you’re passionate about creating robust platforms that empower cutting-edge AI development, join us on our mission!
At Openchip & Software Technologies S.L., we embrace diversity and inclusion. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity.