The Role:
The Accelerator Architecture team is focused on VEC/MATRIX architecture and potentially CPU/Scalar architecture.
Specifically, team will define the VPU and MPU architecture and all the micro-architecture choices using performance and power and area analysis, and providing the SoC team with design guidelines for the specific application.
As an Accelerator AI Architecture Staff Engineer, you will be pivotal in the research, definition, and exploration of core microarchitectural specifications for cutting-edge VPU (Vector Processing Unit) and MPU (Matrix Processing Unit) architectures for next-generation System-on-Chip (SoC) designs, with a strong emphasis on hardware-software co-design principles.
Key responsibilities:
Your responsibilities will involve architecting critical components such as processing lanes, vector register files, and high-bandwidth inter-lane communication networks, with a focus on achieving optimal performance across the VPU, MPU, and CPU for demanding AI and system-level workloads. This includes deeply analyzing and defining the microarchitectural aspects necessary to maximize computational efficiency and overall system throughput, while also considering the implications for software programmability and efficient mapping of AI algorithms.
In this team your responsibility will include, but not limited, to:
- Lead the definition of innovative and high-performance architectures for VPU (Vector Processing Unit) and MPU (Matrix Processing Unit) that significantly improve PPA (Performance-Power-Area), proactively integrating customer needs and anticipating future requirements.
- Spearhead the architectural development of advanced VPU and MPU designs, driving key microarchitectural decisions and ensuring alignment with overall system goals and performance targets.
- Architect and strategically optimize the seamless integration of the VPU and MPU with the scalar CPU, leading efforts to identify and resolve data transfer bottlenecks through innovative hardware and software co-design methodologies. This includes defining efficient communication protocols and considering the software programming models to maximize system throughput for AI workloads.
- Drive research and exploration of novel architectural concepts for next-generation AI accelerators, contributing to the long-term technology roadmap and ensuring competitive performance and efficiency.
- Provide technical leadership and guidance in the evaluation of VPU and MPU architectural implementations, ensuring adherence to design specifications, power constraints, and efficient software utilization.
- Champion software-hardware co-design initiatives to ensure optimal interaction and performance across the entire system, considering the software stack and application requirements from the early architectural stages.
Required Qualifications:
- 10+ years of extensive experience leading architectural efforts in CPU, MPU, or VPU design, with a strong focus on high-performance AI accelerators and software-hardware co-design.
- Expert-level understanding of scalar and vectorial processor architectures, with deep specialization in AI/ML-optimized architectures and their interaction with software stacks.
- Proven expertise in addressing multi-core/many-core accelerator design challenges, including software parallelization, distributed computing, and efficient memory hierarchy design.
- In-depth knowledge of RISC-V architecture and its strategic application in custom AI accelerator development, considering hardware and software aspects.
- Extensive experience in utilizing advanced functional and performance simulators for architecture exploration, validation, and performance projection, including modeling complex software workloads.
- Demonstrated ability to define and drive processor micro-architecture decisions, optimizing performance, power, and area trade-offs for AI acceleration within the broader software ecosystem.
- Significant experience in architecting and delivering high-performance AI accelerators for diverse applications, emphasizing software programmability and performance optimization across key AI frameworks (e.g., TensorFlow, PyTorch, ONNX).
- Strong familiarity with AI/ML software frameworks and a deep understanding of their mapping onto hardware, enabling effective co-design and optimization.
- Proven ability to research and contribute to the definition of innovative next-generation AI accelerator architectures.
- Excellent understanding of SoC design principles and the integration of accelerators, CPUs, and memory subsystems.
Soft Skills:
- team players that focus on the outcome of the team above the individual needs, with respect and honest challenge. Individuals are encouraged to work well with the team.
- good communication and enjoy working with your teammates
- you strive to do your best to provide unique products for our customers.
We are looking for outstanding people willing to join our mission to change this industry and help to build a better world.
If you feel identified with Openchip, please contact us. We can offer a competitive compensation package in a flexible work schema that will help you to keep a balance between your personal and professional life.
At Openchip & Software Technologies S.L., we believe a diverse and inclusive team is the key to groundbreaking ideas. We foster a work environment where everyone feels valued, respected, and empowered to reach their full potential – regardless of race, gender, ethnicity, sexual orientation, or gender identity
